Attempts to extend Moore's Law by introducing new optical and electrical functionalities to the CMOS platform, realization of high-efficiency solid state lighting, manufacturing of concentrator photovoltaic cells, the fabrication of imaging detectors, especially for high-energy electromagnetic and particle radiation, and the fabrication of thermo-electric devices all require—in one form or another—the integration of crystalline materials with dissimilar lattice parameters on top of each other. This can occur basically in two different ways, either by wafer bonding or by “heteroepitaxial growth”. This application belongs to the second method of combining materials, especially to materials the lattice parameters of which differ by more than a few tenths of a percent, and which may widely differ in their thermal expansion coefficients.
Problems Related to Lattice Mismatch
When two mismatched materials are grown epitaxially on top of each other, their difference in lattice parameter (misfit) results in mechanical stress, which, when exceeding a certain limit, is relieved either by elastic or plastic relaxation. Under normal circumstances, when a deposit with sufficiently large misfit is made on a single crystalline substrate, stress relaxation can occur elastically, by means of surface corrugation, for example in the form of islands. Elastic relaxation cannot, however, proceed on a flat film. By contrast, for lower misfit, an epitaxial film may remain flat, while stress is relieved plastically by so-called misfit dislocations, once a certain critical film thickness has been exceeded. Eventually, no matter how large the misfit, plastic relaxation by interfacial misfit dislocations always occurs. Whenever an interface with a significant density of misfit dislocations is incorporated in the active region of a device, e.g., a transistor, its performance may be degraded to a large extent. Interfaces containing misfit dislocations therefore usually need to be spatially separated from the active region of a device. Unfortunately, however, keeping interfaces with misfit dislocations at a distance from the active region of a device often does not guarantee its proper performance. In fact, it rarely happens that dislocations are localized exclusively at the interface between the two materials in the form of misfit dislocations. Misfit dislocations are usually rather accompanied by threading arms extending to the surface of the growing film. Also these threading dislocations can be very detrimental to the functioning of a device if they traverse the active region of a heteroepitaxially grown layer stack. The density of threading dislocations should therefore in general be kept as low as possible.
Problems Related to Thermal Expansion Mismatch
The dislocation problem, arising from the lattice misfit, is not the only obstacle to be overcome when epitaxially growing dissimilar materials on top of each other. In many instances the mismatch of the thermal expansion coefficients is equally serious, especially when layers with relatively large thicknesses are needed, for example in devices like high-brightness light emitting diodes for general lighting purposes, multiple junction solar cells, radiation detectors, thermoelectric generators, and many more.
The mismatch of thermal expansion coefficients may lead to wafer bowing upon cooling to room temperature after the epitaxial growth, seriously hampering subsequent processing steps, such as photolithography and patterning, or also further epitaxial growth. The different thermal expansion of epitaxial layers and substrate may even cause the former to crack, either right after epitaxial growth or during any subsequent temperature cycling, which necessarily occurs for example during the operation of concentrator photovoltaic cells (see for example V. K. Yang et al., Journal of Applied Physics 93, 3859 (2003), the entire disclosure of which is hereby incorporated by reference).
The problem of wafer bowing has been addressed in various ways in the past. One approach consisted in introducing interlayers with reduced crystallinity functioning as stress relaxation layers (see for example US patent application number US2008/0308909 to Masahiro Sakai et al., the entire disclosure of which is hereby incorporated by reference). Another approach involved backside coating of the substrate by some material exerting the opposite stress upon wafer cooling (see for example US patent application number US2003/0033974 to Tetsuzo Ueda, the entire disclosure of which is hereby incorporated by reference). Unfortunately, however, reducing wafer bowing may even increase the tendency of the overlayer to crack, because wafer bowing is associated with partial elastic stress relief.
An alternative way for reducing wafer bowing has been described for example in US patent application number US2008/0233716 to Kazuhide Abe, the entire disclosure of which is hereby incorporated by reference. Therein, deep grooves are formed in a silicon carbide film perpendicular to the direction along which bending on a semiconductor wafer occurs, thereby reducing said bending.
In a related approach, a mechanical stress absorbing system has been designed in which about 10 μm deep and 1 μm wide grooves are formed in a support substrate, onto which a nucleation layer is transferred from a transfer substrate by wafer bonding techniques (see for example US patent application number US2006/0216849 to Letertre et al., the entire disclosure of which is hereby incorporated by reference). In order to effectively relieve stress during temperature incursions in thick epitaxial layers grown onto the nucleation layer, a stress absorbing buffer layer is additionally needed underneath the nucleation layer, similar to the interlayer described in US patent application number US2008/0308909 to Masahiro Sakai et al., the entire disclosure of which is hereby incorporated by reference. Stresses are supposed to be absorbed by defect generation, local material displacement or creep, depending on the nature of the buffer layer. These stress relief mechanisms need to be very effective, when layer cracking and wafer bending are to be eliminated, in case of thick epitaxial layers with large lateral dimensions, i.e., extending essentially across the whole wafer. Material displacement or creep would therefore have to occur over macroscopic distances, which is very unlikely to happen in practice.
The same applies to a related approach in which the relaxation of misfit stress in epitaxial SiGe/Si(001) layers is assumed to occur by a slipping process, the SiGe epilayer thereby remaining cubic. Here, a thin SOI substrate is used instead of a bulk silicon substrate (see for example US patent number U.S. Pat. No. 5,759,898 to Ek et al., the entire disclosure of which is hereby incorporated by reference). Despite of a comparatively low viscosity at sufficiently elevated temperatures, it seems highly unlikely that this slipping process would ever happen on a macroscopic scale.
While wafer bowing and layer cracking are severe practical problems arising typically at layer thicknesses beyond 1 μm, threading dislocations, intimately related to plastic strain relaxation, are normally present already at smaller layer thickness for significant lattice misfits of the order of a fraction of a percent or more.
There have been many attempts to lower threading dislocation densities (TDD) in blanket films, such as compositional grading of buffer layers (see for example US patent number U.S. Pat. No. 5,221,413 to Brasen et al., the entire disclosure of which is hereby incorporated by reference). Alternatively, buffer layers containing high defect densities may facilitate dislocation nucleation and annihilation (see for example H. Chen et al., Journal of Applied Physics 79, 1167 (1996), the entire disclosure of which is hereby incorporated by reference).
Still other methods involve epitaxial growth of parts of a layer at different substrate temperatures, one example being a Ge base layer deposited at low substrate temperature, followed by a second Ge layer at higher temperature (see for example US patent number U.S. Pat. No. 6,537,370 to Hernandez et al., the entire disclosure of which is hereby incorporated by reference). The idea behind this was to suppress or at least reduce island formation by the Stranski-Krastanow mechanism at the early stage of growth, since merging islands and rough surfaces result in larger TDDs.
In addition, post-growth thermal annealing was shown to enhance dislocation glide and annihilation. Cyclic thermal annealing appears to be particularly efficient. Here, the temperature is cycled between a first value above the brittle/ductile transition (i.e., close to the melting point of the epitaxial layer) and a second value below the first. A significant reduction of the TDD was observed for example in Ge films epitaxially grown on Si(001) substrates by using this procedure (see for example U.S. Pat. No. 6,635,110 to Luan et al., the entire disclosure of which is hereby incorporated by reference). The method does not, however, solve the problem of wafer bowing and crack formation, when Ge in the form of blanket films is grown to substantial thicknesses of several micrometers, and the TDD still remains very high, of the order of typically 2-107 cm−2 for 1 μm thick films.
Problem Solving by Limited Area Epitaxy Using Dielectric Masks
Whenever epitaxial layers are grown in the form of continuous films onto a substrate characterized by a significant lattice and thermal expansion mismatch, one is faced with the problems of excessive TDD as soon as the misfit strain starts relaxing plastically, as well as wafer bowing and crack formation at larger thicknesses.
It was realized long ago that a significant further reduction of TDDs can only be achieved by reducing the epitaxial growth area, i.e., by making the epitaxial structures small. This can be achieved by providing the substrate with a dielectric mask, exposing the substrate surface only within openings previously defined by lithography and etching. The idea behind is, that with sufficient layer thickness, threading arms arising from the interface will exit the sides of the epitaxial structure, rather than reaching the upper surface.
The concept was applied to various semiconductor combinations, such as Si, Ge, III-V materials, II-VI materials (see for example UK patent application number GB2 215 514 to Goodfellow et al.). Similarly, the concept was applied to GaAs mesas grown into oxide openings on Si(001) by molecular beam epitaxy (MBE) or chemical vapour deposition (CVD), any material deposited on the oxide mask being removed in a chemical etching step (see for example U.S. Pat. No. 5,158,907 to Fitzgerald, the entire disclosure of which is hereby incorporated by reference). The technique, also termed “epitaxial necking”, was shown to be effective not only in reducing TDDs in GaAs mesas grown on Si by MBE, but also in eliminating cracks (see for example Fitzgerald et al., Journal of Electronic Materials 20, 839 (1991), the entire disclosure of which is hereby incorporated by reference).
The idea of causing defects to terminate at non-crystalline sidewalls, has, in addition to “epitaxial necking”, become known also under the name of “Aspect ratio trapping (ART)” (see for example International patent application number WO2008030574 to Bai et al., the entire disclosure of which is hereby incorporated by reference). Limiting the epitaxial growth area, in combination with the cyclic thermal annealing mentioned before, was also shown to lead to a drastic reduction of TDDs in Ge mesas grown epitaxially on Si(001) (see for example US patent number U.S. Pat. No. 6,635,110 to Luan et al., the entire disclosure of which is hereby incorporated by reference).
Limited area epitaxy, even when combined with thermal annealing, is not, however, sufficient by itself for complete removal of threading dislocations, even when feature sizes are kept very small. To understand this, it is necessary to consider the nature of the dislocations. In cubic semiconductors the most common dislocations are so-called 60-degree dislocations, where Burgers vectors and dislocation lines enclose an angle of 60 degrees with one another, and are both located in {111} glide planes (see for example Blakeslee, Mat. Res. Soc. Symp. Proc. 148, 217 (1989), the entire disclosure of which is hereby incorporated by reference). Such dislocations can reach the edge of epitaxial regions by gliding under the influence of stress, or simply reach the interface to the dielectric once the epitaxial structure is sufficiently high, such that their glide plane no longer cuts through the growth front. There are, however, also so-called sessile dislocations with dislocation lines perpendicular to the interface. They are not affected by stress, and can only be induced to deflect from their vertical orientation by interacting with inclined surface facets. It has indeed been shown that the mechanism of dislocation deflection is present in facetted GaN islands, and can lead to a significant reduction of the TDD (see for example Knoke et al., J. Cryst. Growth 310, 3351 (2008), the entire disclosure of which is hereby incorporated by reference). Surface faceting is expected to have the same effect for group IV and for compound semiconductors (see for example International patent application number WO2008030574 to Bai et al., the entire disclosure of which is hereby incorporated by reference).
Instead of forming limited epitaxial regions in the form of mesas it has been argued that large area heteroepitaxy of mismatched materials with low TDDs should be possible by introducing dislocation sinks in the form of substrate pits. This provides the additional advantage of substantially planar surfaces (see for example European patent application number EPO 505 093 to Bean et al., the entire disclosure of which is hereby incorporated by reference).
A further extension of the technology of TDD reduction involved combining the described patterning by means of dielectric masks with selective epitaxy, followed by epitaxial lateral overgrowth (ELO). For the example of Ge on Si(001) it was argued that by continuing the process until coalescence one may hope to obtain essentially defect-free blanket films (see for example Langdo et al., Applied Physics Letters 76, 3700 (2000), the entire disclosure of which is hereby incorporated by reference). Obviously, however, the problems of wafer bowing and layer cracking would come into play upon increasing the layer thickness further.
In addition, for epitaxial necking to be efficient, the aspect ratio between the height and width of the mask openings should at least be approximately equal to one. For films with thicknesses below about 1 μm it is therefore necessary to use submicron-lithography for defining the size of the mask openings. Even smaller dimensions of the openings are required when elastic relaxation is to contribute significantly to the relaxation of the misfit strain (see for example US patent application number US2008001169 to Lochtefeld et al., the entire disclosure of which is hereby incorporated by reference).
All methods relying on the epitaxial growth into dielectric windows are furthermore limited by the heights of window sidewalls, since the masks cannot be made arbitrarily thick. This also limits the heights of the regions where dislocation trapping may occur.
Still an alternative approach involved the use of selective epitaxial growth on protrusions of crystalline substrate material surrounded by a dielectric mask rather than growth into pits formed in such a mask. In this approach, a buffer layer of Si nanowires is formed on a Si substrate, the nanowires standing perpendicular to the substrate surface and being surrounded by dielectric material through which they protrude. A compound semiconductor is selectively deposited onto the nanowire tips, followed by ELO until a continuous compound semiconductor layer is formed (see for example US patent application number US2008149941 to Li et al., the entire disclosure of which is hereby incorporated by reference). While this approach may as well be effective in reducing the TDD in the compound semiconductor layer, it cannot eliminate the problems associated with the thermal mismatch, when the compound semiconductor layer extends across the whole wafer. As described before, the compound semiconductor layer would have to slip across the substrate over macroscopic distances during cooling from the growth temperature. This is not likely to happen in practice, since neither is a dielectric layer arbitrarily soft, nor could the Si nanowires withstand the shear forces occurring during cooling.
The technology described above, i.e., substrate patterning allowing for “epitaxial necking” or ART, has been applied to the fabrication of electronic and optoelectronic devices made from lattice mismatched materials (see for example US patent application number US2009039361 to Li et al., the entire disclosure of which is hereby incorporated by reference).
The possibility to replace Ge-wafers by Si-wafers as substrates for multi-junction solar cells has been identified as another important application of ART. This application implies the epitaxial growth of relatively thick layer stacks, unless cells are grown on both sides of the substrate. In this latter approach, taking the example of a triple-junction cell, the sub-cell with an intermediate bandgap of about 1.1 eV is made from the Si substrate, while the sub-cell with the largest bandgap is typically made from InGaP, by an ART process applied for example to the top surface, as well as the sub-cell with the smallest bandgap by another ART process on the bottom surface of the substrate (see for example US patent application number US2009065047 to Fiorenza et al., the entire disclosure of which is hereby incorporated by reference). The approach of fabricating sub-cells on both sides of a Si-wafer minimizes the problem of thermal layer cracking because of relatively thin epilayers. The narrow trenches of 300-500 nm typically used in ART may in addition allow for some elastic relaxation, as well as the somewhat compliant nature of the SiO2 mask. In view of frequent thermal cycling during solar cell operation, it may, however, still be disadvantageous to have a structure composed of laterally varying thermal properties. Moreover, the concept requires the use of wetting layers, which, in addition to the dislocation trapping regions, absorb some of the solar radiation, thus lowering the cell efficiency.
The problems with thermal mismatch appear to become even more significant when multi-junction solar cells are grown on the same side of a Si substrate by using ART and ELO processes. It has been suggested to replace the conventional triple-junction cell, featuring a bottom sub-cell made from Ge, by a triple-junction in which all sub-cells are made entirely from III-V materials (see for example International patent application number WO2010033813 to Fiorenza et al., the entire disclosure of which is hereby incorporated by reference). Although the Ge no longer acts as an active material in this type of cell, it was nevertheless suggested to form first a coalesced Ge layer by an ART+ELO process, before growing the active III-V layer stack. Coalescence is, however, accompanied by the generation of large TDDs in the regions where the growth fronts from neighbouring windows meet. This serious problem encountered in continuous layer formation by ART+ELO has not been solved to date (see for example Fiorenza et al., ECS Transactions 33, 963 (2010), the entire disclosure of which is hereby incorporated by reference). Furthermore, the coalesced Ge layer and the active III-V layers together, are necessarily at least 5 μm thick, such that wafer bowing and layer cracking must be expected to become serious obstacles during further device processing and solar cell operation.
Growth on Mask-Less Patterned Surfaces
Approaches Leading to Continuous Layers
In an alternative class of patterning procedures the dielectric mask material is removed from the substrate wafer before epitaxial growth begins, or, alternatively, the patterning is performed without any mask at all. For Si substrates this is possible by using an electrochemical process called anodization, by means of which porous Si is formed. Such porous Si substrates have been used in the fabrication of group III nitride layers, with a Ge layer deposited on the porous Si substrate before the compound semiconductor layers (see for example US patent application number US2005199883 to Borghs et al., the entire disclosure of which is hereby incorporated by reference). The Ge interlayer was believed to reduce the thermal stress arising from the difference in thermal expansion parameters of the Si substrate and group III-nitride material. The porous Si layer on the other hand should accommodate the large lattice mismatch of the Si substrate and the nitride layer. As a result, fewer dislocations should be present in the nitride film, and layer cracking and substrate bowing should be avoided. While these arguments are valid on a small scale, they have to fail to a large extent on a wafer scale, since a continuous group III-nitride layer would have to slip across the substrate by macroscopic distances during cooling from the growth temperature.
Alternatively, an epitaxial layer may be grown on a flat substrate first. Hereafter, stripes are etched into the layer in a manner in which part of the substrate is removed in between the remaining stripes. In a following selective growth process the material grows laterally from the remaining stripes, forming a suspended film over the etched substrate regions. The process, termed “pendeo-epitaxy”, was first applied to epitaxial GaN layers on SiC substrates (see for example T. Zheleva et al., Journal of Electronic Materials 28, L5 (1999), the entire disclosure of which is hereby incorporated by reference). While TDDs can be drastically reduced by the pendeo-epitaxy process, the problems associated with the thermal expansion mismatch remain for the same reasons as in all other approaches in which continuous layers are eventually formed on a thermally mismatched substrate.
In a further approach, the substrate was patterned in a way such as to form an array of weak posts of submicron size and with an aspect ratio above 0.5. A continuous GaN layer was then grown on top of the posts by pendeo-epitaxial methods (see for example US patent number U.S. Pat. No. 6,380,108 to Linthicum et al., the entire disclosure of which is hereby incorporated by reference). The weak posts are configured to crack due to the thermal expansion coefficient mismatch between the substrate and the GaN layer. Upon cooling from the growth temperature at least some of the weak posts should hence crack, thereby relieving stress in the GaN layer. The problem here is again that in order to be effective on a wafer scale, the majority of the posts would have to crack, leading to layer separation from the substrate. While this may indeed be desirable in some applications, it is inconceivable to avoid layer separation and yet release the stress on a wafer scale, again for the same reasons as explained above.
Approaches Involving Nanorods
As explained above, irrespective of the details of the fabrication procedure it has hardly been possible by prior art techniques to substantially reduce the TDD, and eliminate layer cracking and wafer bowing in the case of continuous layers, unless the total layer thickness is kept comparatively low. Upon relaxing the limited film thickness constraint, the only option to tackle all of these problems appears therefore to be one in which layer coalescence is avoided altogether. Besides providing a solution to the practical problems of layer cracking, wafer bowing and dislocation reduction, the use of discontinuous films may have other advantages. One such advantage is the possibility to employ larger In contents in the active layer of group III-nitride LEDs, without deteriorating the internal quantum efficiency, and, simultaneously achieving higher light extraction efficiency, as shown for InGaN quantum well active regions incorporated into GaN nanorods (see for example US patent application number US2007077670 to Kim et al., the entire disclosure of which is hereby incorporated by reference).
In the latter example a GaN buffer layer was first grown on planar sapphire wafers by an MOCVD process known to those working in the field. The nanorods were subsequently formed by using low substrate temperatures favouring vertical over lateral growth.
Instead of letting nanorods nucleate spontaneously, precise position control of nano-LEDs was obtained by patterning a substrate prior to nitride semiconductor growth. This has been demonstrated for example on Si(111) substrates, patterned in the form of an array of pillars of submicron size, and a height of about 5 μm. In this prior art the height of the epitaxial structures formed on mask-less substrates was comparatively small (less than 2 microns) and MOCVD deposition occurred equally in between the Si pillars (see for example Fondling et al., Physica Status Solidi A 206, 1194 (2009), the entire disclosure of which is hereby incorporated by reference). For the AlGaN/InGaN material system nitrogen-rich growth conditions and plasma-assisted MBE are necessary to favour vertical with respect to lateral growth rates to the extent necessary for nanowires to grow (see for example Stoica et al., small 4, 751 (2008), the entire disclosure of which is hereby incorporated by reference). For many devices it is, however, desirable to achieve structure heights of more than a micron. Some devices even require considerably larger height (or layer thickness), such as multiple-junction solar cells, especially for example triple junction solar cells of the conventional kind with Ge forming the bottom sub-cell. Yet taller structures of dozens of microns are necessary for example for X-ray detection.
An attractive way to achieve columnar growth in the AlGaN/InGaN material system has been found to be possible by means of low-energy plasma-enhanced vapour phase epitaxy (LEPEVPE) (see for example WO2006097804 to von Karla the entire disclosure of which is hereby incorporated by reference).
It is an object of the present invention to provide means by which lattice matched and lattice mismatched semiconductor layers can be grown epitaxially in a mask-less process on pre-patterned substrates.
It is another object of the present invention to provide means by which semiconductor layers can be grown epitaxially in a mask-less process on pre-patterned substrates with different thermal expansion coefficients.
It is another object of the present invention to provide means by which lattice mismatched semiconductor layers with a low threading dislocation density can be grown epitaxially in a mask-less process on pre-patterned substrates.
It is another object of the present invention to provide means by which thermally mismatched, crack-free semiconductor layers can be epitaxially grown in a mask-less process on pre-patterned substrates.
It is another object of the present invention to provide means by which thermally mismatched semiconductor layers can be grown in a mask-less process on pre-patterned substrates without causing substrate bowing.
It is another object of the present invention to provide means by which growth of lattice and thermally mismatched semiconductor layers is restricted to the elevated regions of pre-patterned substrates.
It is another object of the present invention to provide means for fabricating semiconductor light emitting diode structures, monolithically integrated on thermally and lattice mismatched, pre-patterned substrates in a mask-less process.
It is another object of the present invention to provide means for fabricating microelectronic circuits monolithically integrated on thermally and lattice mismatched, pre-patterned substrates in a mask-less process.
It is another object of the present invention to provide means for fabricating semiconductor laser structures, monolithically integrated on thermally and lattice mismatched, pre-patterned substrates in a mask-less process.
It is another object of the present invention to provide means for fabricating imaging detectors, such as infra-red and X-ray pixel detectors, monolithically integrated on thermally and lattice mismatched, pre-patterned substrates in a mask-less process.
It is another object of the present invention to provide means for fabricating thermo-electric devices monolithically integrated on thermally and lattice mismatched, pre-patterned substrates in a mask-less process.
It is another object of the present invention to provide means for fabricating multi-junction solar cells, monolithically integrated on thermally and lattice mismatched, pre-patterned substrates in a mask-less process.
It is another object of the present invention to provide means for monolithically integrating devices requiring lattice and/or thermally mismatched semiconductor layers onto pre-patterned, CMOS-processed substrates in a mask-less process.
It is another object of the present invention to provide means for monolithically integrating devices requiring lattice and/or thermally mismatched semiconductor layers in a back-end CMOS-process.